1. Field of the Invention
Embodiments of the present disclosure relate to display technology, and more particularly to a pixel cell and an active matrix liquid crystal display (AMLCD).
2. Discussion of the Related Art
FIG. 1 is a schematic view of a typical AMLCD. As shown in FIG. 1, the AMLCD 10 includes a plurality of pixel cells. Each pixel cell includes a thin-film transistor. For example, the pixel cell P1 includes the thin-film transistor T1, and the pixel cell P2 includes the thin-film transistor T2.
In the manufacturing process of the AMLCD 10, the overlay shift may exist between the drain and the gate of the thin-film transistor in different exposure locations due to exposure precision. Thus, the thin-film transistor in different locations may have different parasitic capacitance.
FIG. 2 is an enlarged view of the thin-film transistor T1 and thin-film transistor T2 of FIG. 1. As shown in FIG. 2, the parasitic capacitance generated from the overlay shift of the gate and the source of the thin-film transistor T1 is Cgd1, and the parasitic capacitance generated from the overlay shift of the gate and the source of the thin-film transistor T2 is Cgd2. As the overlay areas (shaded portion) of the thin-film transistor T1 and the thin-film transistor T2 are not the same, the gray levels of the pixel cell P1 and that of the pixel cell P2 are not the fame. Thus, the display performance is not good due to Mura effect, image flicker, and so on.